Priority is claimed to Korean Patent Application No. 2003-38521, filed on Jun. 14, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a vertical carbon nanotube (CNT)-field effect transistor (FET) and a method of manufacturing the same, and more particularly, to a vertical CNT-FET employing a CNT channel surrounded by a gate and a gate insulating layer and a method of manufacturing the same.
2. Description of the Related Art
As the integration density of semiconductor devices increases, traditional complementary metal oxide semiconductor (CMOS) technology reaches limits of scaling. High integration, high performance, and low power dissipation are achieved by reducing the dimensions of CMOS devices. This trend comes with decreases in the width and length of a gate electrode, an isolation area between unit elements, and thickness and junction depth of a gate insulating layer.
Good gate controllability must be provided by maximizing a ratio of on-current to off-current for scaling CMOS devices. According to the 2001 International Technology Roadmap for Semiconductors (ITRS), various three-dimensional (3-D) silicon (Si) transistors are being explored to improve drive current. These include ultra-thin body fully depleted silicon-on-insulator (UTB-FD SOI) transistors on a SOI substrate [S. Fung et al., IEDM-2000, p.629], band-engineered transistors [K. Rim, et al., VLSI 2002 page 12] that uses a strained Si channel to increase electron mobility, vertical transistors [Oh, et al., IEDM-2000, page 65], Fin-FETs [Hisamoto, et al., IEEE Trans. On Electron Device 47, 2320 (2000)], and double-gate transistors [Denton, et al., IEEE Electron Device Letters 17, 509 (1996)].
However, in a Si transistor employing a 3-D gate structure, it is difficult to modify the structure of a gate in such a manner that maximizes the effect of electric field produced by a gate. In particular, a process for forming a 3-D gate structure becomes complicated since a Si substrate or Si layer with a 3-D structure produced by deposition and patterning is used as a channel.
In recent years, a transistor employing a CNT as a channel has been proposed to overcome scaling limits encountered by Si devices. Tans and Dekker reported a room-temperature transistor based on a CNT [Tans, et al., Nature 393, 49 (1998)]. Particularly, research is being actively conducted to apply CNT growth in horizontal direction [Hongjie Dai, et al., Appl. Phys. Lett. 79, 3155 (2001)] and CNT growth from nanoholes in vertical direction [Choi, et al., Adv. Mater. 14, 27 (2002); Duesberg, et al., Nano Letters] to devices. The primary challenge of this research is to develop a CNT transistor structure that is easy to fabricate and provides good gate controllability and a method for fabricating the same.